This invention relates generally to a method of trench isolation used in the fabrication of semiconductor devices, wafers and the like. More specifically, the present invention relates to a method of trench isolation using chemical vapor deposition (CVD) to deposit a trench fill oxide prior to sidewall liner oxidation growth.
Chemical vapor deposition (CVD) methods are widely used in the semiconductor industry to deposit layers or films on the surface of semiconductor substrates. Providing void free gap fill capability of such films has been of extreme interest in the semiconductor industry since the introduction of CVD techniques in the later 1980""s. The unique variable of selective deposition rates dependent upon the specific deposition conditions and surfaces states of the underlying materials have also been extensively studied. Film qualities such as higher density, lower wet etch rate, reduced film shrinkage, and improved gap fill, were all found to improve as pressure increased from sub-atmospheric to atmospheric, as deposition temperature increased, and as TEOS:Ozone ratios decreased in the CVD process.
In 1994, West et al, first studied the behavior of the atmospheric pressure CVD (APCVD) process using TEOS:Ozone to deposit films on the underlayers of trench isolation modules, namely Si3N4, thermal oxide, and bare silicon. Deposition rates were shown to vary as a function of surface states: i.e. surfaces that are non-treated, plasma fluorine and plasma chlorine treated. This work demonstrated that TEOS:Ozone selective deposition for trench isolation was feasible, but the presence of fluorine was shown to dramatically modify the deposition rates from the high ozone regime, more than doubling the deposition rate of the Si3N4.
FIG. 1 shows a typical cross section of a structure on a semiconductor substrate, captured after a series of process steps. Trenches are formed between the interconnecting lines or device features, and these trenches are filled by depositing an insulating material, called xe2x80x9ctrench isolationxe2x80x9d and/or xe2x80x9ctrench fill oxidexe2x80x9d in order to isolate the lines or features. Prior art trench isolation processes typically consist of a sequence of laying down a pad oxide layer, followed by a mask nitride layer, which is then etched through to form trenches in the silicon substrate. An oxide layer is grown onto the trench""s sidewalls (also called a sidewall or oxide liner or a thermal oxide), and subsequently the trench is filled by depositing an oxide. The film is then annealed and planarized.
This prior art process creates the sidewall liner prior to filling the trench with a deposited oxide. This technique can result in a poor quality oxide layer fill in the trench or gap. This poor quality gap fill is shown in FIGS. 2a and 2b. Specifically, variable trench sidewall oxidation rates occur due to crystal orientation effects on oxidation rates and the oxidation-related viscoelastic stress. This can cause higher oxidation rates at the top of the trenches compared to the bottom/base of the trenches, and when combined with near vertical (i.e. about 80-85xc2x0) sidewall angles which provide a vertical to re-entrant sidewall profile that cannot be filled without leaving voids during the trench fill oxide deposition process.
In addition, growth of the oxide liner prior to the deposited oxide often results in a stress mismatch between the deposited trench fill oxide and the liner, and during later process steps causes cracks, or increased wet etch rate, between the film layers.
As the density of devices packed on a semiconductor substrate increase, the aspect ratio of the gaps or trenches also increases. To fill gaps and/or trenches of approximately 3:1 aspect ratio with spaces  less than 0.25 micron, the use of a technique known as High Density Plasma (HDP) has been used in the prior art. While much effort has been spent on HDP, this technique has not shown the capability to provide good quality films beyond 3:1 aspect ratios, nor has it been successful with re-entrant structures. Further, the HDP process often damages the wafer.
Another gap fill technique that has been used is the Spin-On-Glass (SOG) process by which a liquid is applied to the semiconductor structures, spun at high speed to distribute the material across the structures, then heat treated to cure or stabilize the resultant film. This technique shows excellent gap fill capability but adversely suffers excessive shrinkage of the material due to the required heat treatment and is therefore not acceptable as an isolation material.
Another prior art technique known as the dispersion or showerhead CVD process, such as that described in WIPO Patent Application No. WO98/03991 has been used, but is limited and cannot fill structures of greater than 3 to 4:1 aspect ratios at or below 0.25 micron gaps. This prior art technique has utilized a xe2x80x9cshowerheadxe2x80x9d reactant distribution in which the reactants are pre-mixed prior to delivery through a showerhead type injector. The lack of precise control over the delivery of the reactants and subsequent oligomer formation and removal, causes voids in films deposited on structures having greater than 4:1 aspect ratios.
Additionally a dispersion head atmospheric pressure CVD (APCVD) process is known as a gap fill process, but it also suffers from the same gap fill limitations as the showerhead process in that the intermediate reactants are pre-mixed, and precise control of the reactants is not possible.
As illustrated by the aforementioned limitations of the prior art techniques, there is a need for an improved process for trench isolation.
Elbel et al, xe2x80x9cA New STI Process Based on Selective Oxide Deposition,xe2x80x9d 1998 Symposium on VLSI Technology Digest of Technical Papers, IEEE, page 208.
Elbel et al, xe2x80x9cMethod of Producing a Buried, Laterally Insulated Zone of Very High Conductivity in a Semiconductor Substrate,xe2x80x9d International Patent Application PCT/DE97/01542, filed Jul. 22, 1997; international disclosure date Jan. 29, 1998.
West et al, xe2x80x9cAPCVD TEOS:Ozone Thin Film Integration into Multilevel Interconnect Process Modules,xe2x80x9d VMIC (1994).
Fischer et al, xe2x80x9cGlobal Planarization by Selective Deposition of Ozone/TEOS,xe2x80x9d 1995 VMIC Conference, page 247.
Suzuki et al, xe2x80x9cMethod of Producing semiconductor integrated circuit device having interlayer insulating film covering substrate,xe2x80x9d U.S. Pat. No. 5,491,108, Feb. 13, 1996.
Bohr, Mark, xe2x80x9cIsolation structure formation for semiconductor circuit fabrication,xe2x80x9d U.S. Pat. No. 5,536,675, Jul. 16, 1996.
Kameyama, xe2x80x9cMethod for manufacturing semiconductor device,xe2x80x9d U.S. Pat. No. 4,472,240, Sep. 18, 1984.
Grassl et al, xe2x80x9cProcess for Planarizing a Substrate Surface,xe2x80x9d International Patent Application PCT/EP97/04697, filed Aug. 28, 1997; International disclosure date Mar. 5, 1998.
Vassiliev V. et al., xe2x80x9cProperties and Gap Fill Capability of HDP-PSG Films for 0.18 micron Device Applications and Beyond, Dumic Conf 1999, pp. 235-244.
Nag S. et al., xe2x80x9cComparative Evaluation of Gap Fill Dielectrics in Shallow Trench Isolation for Sub 0.25 microns Technologies IEDM, 1996, pp. 841-844.
Xia L-Q. et al., xe2x80x9cSelective Oxide Deposition for Shallow Trench Isolation.
Accordingly, it is an object of the present invention to provide an improved method of trench isolation.
The inventors have discovered a trench isolation method whereby contrary to the prior art, the trench is filled first with a deposited oxide layer (i.e. the trench fill oxide), and because the oxide liner (which is non-conformal) is not present on the sidewalls of the trench, the trench fill is more likely to be void free. Deposition at atmospheric or near atmospheric (200 Ton or 1 atm) pressure using linear reactant delivery also improves the trench fill, as compared to sub-atmospheric dispersion reactant delivery trench fill depositions. After the deposition of the trench fill oxide, the substrate is placed in a densification/oxidation tube furnace or Rapid Thermal Process (RTP) system where growth of a thermal oxide layer or liner occurs on the sidewalls of the trench (the thermal oxide layer or liner is also referred to as a xe2x80x9csidewall linerxe2x80x9d or xe2x80x9cthermal oxide linerxe2x80x9d). In a preferred embodiment of the present invention, growth of the thermal and densification are performed simultaneously.
A key aspect of the present invention is thus the order of the process steps and the combination of two effects (growth of the thermal oxide and film densification) into one process step, with a resulting significant and unexpected improvement in the ability to ensure void free gaps.
In another aspect of the present invention is a method of forming a film on the surface of a semiconductor substrate having one or more trench isolation structures with sidewalls formed thereon, comprising the steps of: depositing an oxide film by chemical vapor deposition (CVD) using ozone and a silicon containing reactant atop the trench structure and sidewalls; and after the depositing step, growing a thermal oxide on the surface of the sidewalls. Preferably, any native or chemical oxide is removed from the side walls which improves the surface selectivity. Preferably the film is densified while growing the thermal oxide.
In yet another aspect of the present invention the step of depositing an oxide film in the trenches is carried out such that the oxide film may be conformal, near-conformal, or non-conformal. Further, the present invention provides for the formation of a substantially planar surface which acts to reduce the complexity of subsequent chemical mechanical planarization (CMP) process, and in some instances may eliminate the need for CMP altogether.